Artificial intelligence is progressing ever faster with new applications and results that would not be possible only a few years ago. At the same time, hardware security is becoming increasingly important for embedded systems applications where the number of such applications keeps on growing. The connection between AI and hardware security is becoming more prominent. Today, there are numerous applications where AI has either an offensive or defensive role for HW security. AIHWS aims to position itself in the intersection of these topics and provide a space where ideas converge into exciting new approaches for HW security. This workshop will provide an environment for researchers from academic and industrial domains to discuss findings and on-going work on all aspects of hardware security and artificial intelligence including design, attacks, manufacturing, testing, validation, utilization.
We encourage researchers working on all aspects of AI and HW security to take the opportunity and use AIHWS to share their work and participate in discussions.
The authors are invited to submit the papers using EasyChair submission system.
The link for submission will be posted later.
Every accepted paper must have at least one author registered for the workshop. All submissions must follow the original LNCS format with a page limit of 18 pages, including references and possible appendices. Papers should be submitted electronically in PDF format. The post-proceedings will be published by Springer in the LNCS series.
The best workshop paper award is selected from all workshops. Each workshop nominates a candidate paper, and the winning paper is selected among them.
EXTENDED submission deadline!
Workshop paper submission deadline: Apr 1, 2022
previously Mar 21, 2022
Workshop paper notification: Apr 15, 2022
Camera-ready papers for pre-proceedings: May 1, 2022
Workshop date: June 21, 2022
(in parallel with the main conference)
Delft University of Technology, The Netherlands1, Riscure BV, The Netherlands2
Crypto Group, ICTEAM Institute, UCLouvain, Louvain-la-Neuve, Belgium1, SGS Brightsight, Delft, The Netherlands2
Delft University of Technology, The Netherlands1, Radboud University Nijmegen, The Netherlands2
Radboud University, The Netherlands
Mitsubishi Electric Corporation, Kamakura, Kanagawa, Japan1, Ritsumeikan University, Kusatsu, Shiga, Japan2
NXP Semiconductors Germany GmbH, Germany1, Radboud University, The Netherlands2
Organizational leaders know that there is both tremendous opportunity in the data they own . The challenge is responsibly leveraging that data without exposing it. In this session, you’ll learn how Intel is taking data privacy to the next level with homomorphic computing.
We all know data can be encrypted for privacy but deriving value from it typically involves computations that require decryption while the data is in use. Homomorphic computing allows for computation on encrypted data, thereby eliminating vulnerability. The data and resulting computations remain encrypted until the data owner chooses to decrypt it. Intel, in collaboration with Microsoft, has developed technology that provides end-to-end data encryption. In this session, Rosario Cammarota, Principal Engineer at Intel Labs, explains how Intel is paving the way for homomorphic computing with key deployments including the Defense Advanced Research Projects Agency (DARPA) so that organizations can begin applying it sooner rather than later.
Rosario Cammarota is a Principal Engineer in the Emerging Security Lab at Intel Labs. He leads Privacy-Enhanced Computing Research, with a focus on the theory, application, and standardization of processing encrypted data. Ro received his Ph.D. in Computer Science from the University of California (Irvine) in 2013, but his passion for academic research continues till date. He serves as the Organizing Committee Member for several international conferences and workshops in computer security, embedded systems, and high-performance computing, incl. DAC, HOST. He is a Senior Member of IEEE and recipient of the SRC “Mahboob Khan” Outstanding Industry Liaison Award in 2017, 2018, and 2019.
Fault attacks are considered among critical threat to embedded cryptography. This talk will be explore the power of fault attacks along three distinct avenues. We present Persistent Fault Analysis (PFA) and how it can break redundancy based countermeasures and higher order masking with just one fault. PFA also shows great performance under multiple faults. Next, we discuss fault attack on post quantum cryptography with LWE construction under one (or few) fault. We next demonstrate one of the first practical combined attacks (laser + power) on bit permutation based ciphers like PRESENT and GIFT as well as on widely used redundancy countermeasure. Finally we shed light on how faults can be used to disturb deep learning inference.
Dr. Shivam Bhasin is a Senior Research Scientist and Programme Manager (Cryptographic Engineering) at Centre for Hardware Assurance, Temasek Laboratories, Nanyang Technological University Singapore. He received his PhD in Electronics & Communication from Telecom Paristech in 2011, Advanced Master in Security of Integrated Systems & Applications from Mines Saint-Etienne, France in 2008. Before NTU, Shivam held position of Research Engineer in Institut Mines-Telecom, France. He was also a visiting researcher at UCL, Belgium (2011) and Kobe University (2013). His research interests include embedded security, trusted computing and secure designs. He has co-authored several publications at recognized journals and conferences. Some of his research now also forms a part of ISO/IEC 17825 standard.
The program starts at 14:05 pm, CEST time (UTC + 2).
|14:00 - 14:05||Welcome note from the organizers|
|14:05 - 15:05||Keynote talk 1: A Fault Can Do Wonders: On Advanced Fault Attacks on Protection Mechanisms, Post-Quantum Cryptography and Deep Learning
Shivam Bhasin, Temasek Laboratories, Nanyang Technological University, Singapore
|15:05 - 15:30||Towards Isolated AI Accelerators with OP-TEE on SoC-FPGAs
Tsunato Nakai and Daisuke Suzuki and Takeshi Fujino
|15:30 - 15:55||On the Effect of Clock Frequency on Voltage and EM Fault Injection
Stefanos Koffas and Praveen Kumar Vadnala
|15:55 - 16:20||A side-channel based disassembler for the ARM-Cortex M0
Jurian van Geest and Ileana Buhan
|16:20 - 16:30||Break|
|16:30 - 16:55||S-box Pooling: Towards More Efficient Side-Channel Security Evaluations
Yuanyuan Zhou and Francois-Xavier Standaert
|16:55 - 17:20||Order Vs. Chaos: Multi-trunk classifier for side-channel attack
Praveen Kulkarni and Vincent Verneuil
|17:20 - 17:45||Deep Learning-based Side-channel Analysis against AES Inner Rounds
Sudharshan Swaminathan and Łukasz Chmielewski and Guilherme Perin and Stjepan Picek
|17:45 - 18:45||Keynote talk 2: Homomorphic Computing: Achieving the Pinnacle of Data Privacy
Rosario Cammarota, Intel, USA